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NS DESIG R NEW T FO NT PAR NDED OMME ACEME L EC NOT R MENDED REP A Data Sheet COM L9001 RE IS
(R)
ISL9001
March 28, 2008 FN9231.2
LDO with Low ISUPPLY, High PSRR
ISL9001 is a high performance Low Dropout linear regulator capable of sourcing 300mA current. It has a low standby current and high-PSRR and is stable with an output capacitance of 1F to 10F with an ESR of up to 200m. The ISL9001 has a very high PSRR of 90dB and outputs noise less than 30VRMS. A reference bypass pin allows connection of a noise-filtering capacitor for low-noise and high-PSRR applications. When coupled with a no load quiescent current of 25A (typical), and 0.1A shutdown current, the ISL9001 is an ideal choice for portable wireless equipment. The ISL9001 provides a power-good signal with delay time programmable with an external capacitor. Several different fixed voltage outputs are standard. Output voltage options for each LDO range are from 1.5V to 3.3V. Other output voltage options may be available upon request.
Features
* 300mA high performance LDO * Excellent transient response to large current steps * Excellent load regulation: <0.1% voltage change across full range of load current * High PSRR: 90dB @ 1kHz * Wide input voltage capability: 2.3V to 6.5V * Extremely low quiescent current: 25A * Low dropout voltage: typically 200mV @ 300mA * Low output noise: typically 30VRMS @ 100A (1.5V) * Stable with 1F to 10F ceramic capacitors * Soft-start to limit input current surge during enable * Current limit and overheat protection * Delayed POR, programmable with external capacitor * 1.8% accuracy over all operating conditions
Pinout
ISL9001 (8 LD 2x3 DFN) TOP VIEW
VIN EN CBYP CPOR 1 2 3 4 8 VO 7 POR 6 NC 5 GND
* Tiny 2mmx3mm 8 Ld DFN package * -40C to +85C operating temperature range * Pb-free (RoHS compliant)
Applications
* PDAs, cell phones and smart phones * Portable instruments, MP3 players * Handheld devices, including medical handhelds
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL9001 Ordering Information
PART NUMBER (Notes 1, 2) ISL9001IRNZ-T ISL9001IRMZ-T ISL9001IRLZ-T ISL9001IRKZ-T ISL9001IRJZ-T ISL9001IRRZ-T ISL9001IRFZ-T ISL9001IRCZ-T ISL9001IRBZ-T NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Please refer to TB347 for details on reel specifications. 3. For other output voltages, contact Intersil Marketing. PART MARKING EAA EBA ECA EDA EEA EFA EGA EHA EJA VO VOLTAGE (V) (Note 3) 3.3 3.0 2.9 2.85 2.8 2.6 2.5 1.8 1.5 TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 8 Ld 2x3 DFN 8 Ld 2x3 DFN 8 Ld 2x3 DFN 8 Ld 2x3 DFN 8 Ld 2x3 DFN 8 Ld 2x3 DFN 8 Ld 2x3 DFN 8 Ld 2x3 DFN 8 Ld 2x3 DFN PKG. DWG. # L8.2x3 L8.2x3 L8.2x3 L8.2x3 L8.2x3 L8.2x3 L8.2x3 L8.2x3 L8.2x3
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FN9231.2 March 28, 2008
ISL9001
Absolute Maximum Ratings
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V VO Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN+0.3)V ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2500V Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .200V
Thermal Information
Thermal Resistance (Notes 4, 5) JA (C/W) JC (C/W) 8 Ld 2x3 DFN Package . . . . . . . . . . . . 69 10 Junction Temperature Range . . . . . . . . . . . . . . . . .-40C to +125C Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40C to +85C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40C to +85C; VIN = (VO + 0.5V) to 5.5V with a minimum VIN of 2.3V; CIN = 1F; CO = 1F. SYMBOL TEST CONDITIONS MIN (Note 8) TYP MAX (Note 8) UNITS
PARAMETER DC CHARACTERISTICS Supply Voltage Ground Current
VIN Quiescent condition: IO = 0A IDD LDO active LDO disabled @ +25C
2.3
6.5
V
25 0.1 1.9 1.6 2.1 1.8
32 1.0 2.3 2.0 +0.7 +0.8 +1.8
A A V V % % % mA
Shutdown Current UVLO Threshold
IDDS VUV+ VUV-
Regulation Voltage Accuracy
Initial accuracy at VIN = VO + 0.5V, IO = 10mA, TJ = +25C VIN = VO + 0.5V to 5.5V, IO = 10A to 300mA, TJ = +25C VIN = VO + 0.5V to 5.5V, IO = 10A to 300mA, TJ = -40C to +125C
-0.7 -0.8 -1.8 300 350 475 300 250 200 145 110
Maximum Output Current Internal Current Limit Dropout Voltage (Note 7)
IMAX ILIM VDO1 VDO2 VDO3
Continuous
600 500 400 325
mA mV mV mV C C
IO = 300mA; VO < 2.5V IO = 300mA; 2.5V VO 2.8V IO = 300mA; VO > 2.8V
Thermal Shutdown Temperature
TSD+ TSD-
AC CHARACTERISTICS Ripple Rejection (Note 6) IO = 10mA, VIN = 2.8V (min), VO = 1.8V, CBYP = 0.1F @ 1kHz @ 10kHz @ 100kHz Output Noise Voltage (Note 6) IO = 100A, VO = 1.5V, TA = +25C, CBYP = 0.1F BW = 10Hz to 100kHz 90 70 50 30 dB dB dB VRMS
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FN9231.2 March 28, 2008
ISL9001
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40C to +85C; VIN = (VO + 0.5V) to 5.5V with a minimum VIN of 2.3V; CIN = 1F; CO = 1F. (Continued) SYMBOL TEST CONDITIONS MIN (Note 8) TYP MAX (Note 8) UNITS
PARAMETER
DEVICE START-UP CHARACTERISTICS Device Enable Time LDO Soft-start Ramp Rate EN PIN CHARACTERISTICS Input Low Voltage Input High Voltage Input Leakage Current Pin Capacitance POR PIN CHARACTERISTICS POR Thresholds VPOR+ VPORPOR Delay tPLH tPHL POR Pin Output Low Voltage POR Pin Internal Pull-up Resistance NOTES: 6. Limits established by characterization and are not production tested. 7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V. 8. Parts are 100% tested at +25C. Temperature limits established by characterization and are not production tested. VOL RPOR @ IOL = 1.0mA 78 100 CPOR = 0.01F As a percentage of nominal output voltage 91 87 100 94 90 200 25 0.2 180 97 93 300 % % ms s V k VIL VIH IIL, IIH CPIN Informative 5 -0.3 1.4 0.5 VIN + 0.3 0.1 V V A pF tEN tSSR Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO (nom) Slope of linear portion of LDO output voltage ramp during start-up 250 30 500 60 s s/V
EN
tEN VPOR+ VPOR+ VO
VPOR-
VPOR-
tPLH
tPHL
POR
FIGURE 1. TIMING PARAMETER DEFINITION
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FN9231.2 March 28, 2008
ISL9001 Typical Performance Curves
0.8 0.6 OUTPUT VOLTAGE, VO (%) 0.4 0.2 -40C 0.0 +25C -0.2 -0.4 -0.6 -0.8 3.4 3.8 4.2 4.6 5.0 5.4 INPUT VOLTAGE (V) 5.8 6.2 6.6 +85C VO = 3.3V ILOAD = 0mA 0.10 0.08 OUTPUT VOLTAGE CHANGE (%) 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 50 150 250 100 200 300 LOAD CURRENT - IO (mA) 350 400 +85C +25C -40C VIN = 3.8V VO = 3.3V
FIGURE 2. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT)
0.10 0.08 OUTPUT VOLTAGE CHANGE (%) 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 -40 VIN = 3.8V VO = 3.3V ILOAD = 0mA
FIGURE 3. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
3.4 IO = 0mA VO = 3.3V
3.3 OUTPUT VOLTAGE, VO (V)
3.2 IO = 150mA 3.1 IO = 300mA 3.0
2.9
2.8 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 3.1 3.6 4.1 4.6 5.1 5.6 6.1 6.5 INPUT VOLTAGE (V)
FIGURE 4. OUTPUT VOLTAGE CHANGE vs TEMPERATURE
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT)
350
2.9 IO = 0mA 2.8 OUTPUT VOLTAGE, VO (V) VO = 2.8V DROPOUT VOLTAGE, VDO (mV)
300 250 VO = 2.8V 200 VO = 3.3V 150 100 50 0
2.7 IO = 150mA 2.6 IO = 300mA 2.5
2.4
2.3 2.6
3.1
3.6
4.1
4.6
5.1
5.6
6.1
6.5
0
50
100
150
200
250
300
350
400
INPUT VOLTAGE (V)
OUTPUT LOAD (mA)
FIGURE 6. OUTPUT VOLTAGE vs INPUT VOLTAGE (2.8V OUTPUT)
FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT
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FN9231.2 March 28, 2008
ISL9001 Typical Performance Curves
350 VO = 3.3V 300 DROPOUT VOLTAGE, VDO (mV) 250 +85C 200 150 100 50 0 +25C -40C GROUND CURRENT (A) 35 +125C 30 +25C 25 -40C 20 VO = 3.3V 15
(Continued)
40
0
50
100
150
200
250
300
350
400
10 3.0 3.5 4.0 4.58 5.0 5.5 6.0 6.5 INPUT VOLTAGE (V)
OUTPUT LOAD (mA)
FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE
40
200 180
35 160 GROUND CURRENT (A) 140 120 100 80 60 40 20 0 0 50 100 150 200 250 VIN = 3.8V VO = 3.3V +85C -40C +25C GROUND CURRENT (A) 30
25
20 VIN = 3.8V VO = 3.3V ILOAD = 0A
15
300
350
400
10 -40 -25
-10
5
LOAD CURRENT (mA)
20 35 50 65 TEMPERATURE (C)
80
95
110 125
FIGURE 10. GROUND CURRENT vs LOAD
FIGURE 11. GROUND CURRENT vs TEMPERATURE
VO = 2.85V IL = 150mA 5 VOLTAGE (V) 4 3 2 1 0 VO POR VEN (V) VIN VO (V) 3 2 1 0 5 0
VIN = 5.0V VO = 2.85V IL = 150mA CL = 1F CBYP = 0.01F
0
0.5
1.0
1.5
2.0 2.5 TIME (s)
3.0
3.5
4.0
4.5
5.0
0
0.2
0.4
0.6
0.8
1.0 1.2 TIME (ms)
1.4
1.6
1.8
2.0
FIGURE 12. POWER-UP/POWER-DOWN
FIGURE 13. TURN ON/TURN OFF RESPONSE
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FN9231.2 March 28, 2008
ISL9001 Typical Performance Curves
(Continued)
VO = 3.3V ILOAD = 300mA CLOAD = 1F CBYP = 0.01F 4.3V 3.6V 4.2V 3.5V
VO = 2.8V ILOAD = 300mA CLOAD = 1F CBYP = 0.01F
10mV/DIV
10mV/DIV
400s/DIV
400s/DIV
FIGURE 14. LINE TRANSIENT RESPONSE, 3.3V OUTPUT
FIGURE 15. LINE TRANSIENT RESPONSE, 2.8V OUTPUT
1000 SPECTRAL NOISE DENSITY (nV/Hz)
100
VO (25mV/DIV)
VO = 1.8V VIN = 2.8V
10 VIN = 3.6V VO = 1.8V ILOAD = 10mA 1 CBYP = 0.1F CIN = 1F CLOAD = 1F 0.1 10
300mA ILOAD 100A
100
100s/DIV
1k 10k FREQUENCY (Hz)
100k
1M
FIGURE 16. LOAD TRANSIENT RESPONSE
FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY
100 90 80 70 PSRR (dB) 60 50 40 30 20 10 0 100 1k 10k FREQUENCY (Hz) 100k 1M VIN = 3.6V VO = 1.8V IO = 10mA CBYP = 0.1F CLOAD = 1F
FIGURE 18. PSRR vs FREQUENCY
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FN9231.2 March 28, 2008
ISL9001 Pin Description
PIN NUMBER 1 2 3 PIN NAME VIN EN CBYP Supply Voltage/LDO Input: Connect a 1F capacitor to GND. LDO Enable. Reference Bypass Capacitor Pin: Optionally connect capacitor of value 0.01F to 0.1F between this pin and GND to achieve lowest noise and highest PSRR. POR Delay Setting Capacitor Pin: Connect a capacitor between this pin and GND to delay the POR output release after the output reaches 94% of its specified voltage level. (200ms delay per 0.01F). GND is the connection to system ground. Connect to PCB Ground plane. Do not connect. Open-drain POR Output (active-low): Internally connected to VO through 100k resistor. LDO Output: Connect capacitor of value 1F to 10F to GND (1F recommended). DESCRIPTION
4
CPOR
5 6 7 8
GND NC POR VO
Typical Application
ISL9001 VIN (2.3V TO 5V) ON ENABLE OFF 1 VIN 2 EN 3 4 C1 C2 C4 CPOR CBYP 5 GND C3 POR VO 7 8 VOUT OK VOUT TOO LOW VOUT RESET (200ms DELAY, C4 = 0.01F)
C1, C3: 1F X5R CERAMIC CAPACITOR C2: 0.1F X7R CERAMIC CAPACITOR C4: 0.01F X7R CERAMIC CAPACITOR
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FN9231.2 March 28, 2008
ISL9001 Block Diagram
VIN
VO
UVLO
CONTROL LOGIC
SHORT CIRCUIT, THERMAL PROTECTION, SOFT-START
+ EN + 1.0V VO 100k
GND BANDGAP AND TEMPERATURE SENSOR VOLTAGE AND REFERENCE GENERATOR 1.0V 0.94V 0.9V POR DELAY
POR
CBYP
CPOR
GND
Functional Description
The ISL9001 contains all circuitry required to implement a high performance LDO. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9001 adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, and soft-start. Smart Thermal shutdown protects the device against overheating.
During operation, whenever the VIN voltage drops below about 1.84V, the ISL9001 immediately disables the LDO output. When VIN rises back above 2.1V, the device re-initiates its start-up sequence and LDO operation will resume automatically.
Reference Generation
The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. The filter includes the external capacitor connected to the CBYP pin. A 0.01F capacitor connected to CBYP implements a 100Hz lowpass filter, and is recommended for most high performance applications. For the lowest noise application, a 0.1F CBYP capacitor should be used. This filters the reference noise to below the 10Hz to 1kHz frequency band, which is crucial in many noise-sensitive applications. The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference, POR detection thresholds, and other voltage references required for current generation and over-temperature detection. The current generator outputs references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination.
Power Control
The ISL9001 has an enable pin (EN) to control power to the LDO output. When EN is low, the device is in shutdown mode. During this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1A. When the enable pin is asserted, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least about 2.1V. Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry power-up. Once the references are stable, a fast-start circuit quickly charges the external reference bypass capacitor (connected to the CBYP pin) to the proper operating voltage. Once the bypass capacitor has been charged, the LDO powers up.
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FN9231.2 March 28, 2008
ISL9001
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9001 provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1F to 10F output capacitor that has a tolerance better than 20% and ESR less than 200m. The design is performance-optimized for a 1F capacitor. Unless limited by the application, use of an output capacitor value above 4.7F is not recommended as LDO performance improvement is minimal. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30s/V to minimize current surge. The ISL9001 provides short-circuit protection by limiting the output current to about 425mA. The LDO uses an independently trimmed 1V reference as its input. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory.
Overheat Detection
The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about +140C, if the LDO is sourcing more than 50mA it shuts down until the die cools sufficiently. Once the die temperature falls back below about +110C, the disabled LDO is re-enabled and soft-start automatically takes place.
Power-On Reset Generation
The ISL9001 has a Power-on Reset signal generation circuit, which indicates that output power is good. The POR signal is generated as follows. A POR comparator continuously monitors the output of the LDO. The LDO enters a power-good state when the output voltage is above 94% of the expected output voltage for a period exceeding the LDO PGOOD entry delay time (see the following). In the power-good state, the open-drain POR output is in a high-impedance state. An internal 100k pull-up resistor pulls the pin up to the LDO output voltage. An external resistor can be added between the POR output and the LDO output for a faster rise time, however, the POR output should not connect through an external resistor to a supply greater than the LDO voltage. The power-good state is exited when the LDO output falls below 90% of the expected output voltage for a period longer than the PGOOD exit delay time. While power-good is false, the ISL9001 pulls the POR pin low. The PGOOD entry and exit delays are determined by the value of an external capacitor connected to the CPOR pin. For a 0.01F capacitor, the entry and exit delays are 200ms and 25s respectively. Larger or smaller capacitor values will yield proportionately longer or shorter delay times. The POR exit delay should never be allowed to be less than 10s to ensure sufficient immunity against transient induced false POR triggering.
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FN9231.2 March 28, 2008
ISL9001 Dual Flat No-Lead Plastic Package (DFN)
2X 0.15 C A A D 2X 0.15 C B
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A
E
MIN 0.80 -
NOMINAL 0.90 0.20 REF
MAX 1.00 0.05
NOTES -
A1 A3 b D
6 INDEX AREA B
0.20
0.25 2.00 BSC
0.32
5,8 -
TOP VIEW
D2 E
// 0.10 C
1.50
1.65 3.00 BSC
1.75
7,8 -
E2
A 0.08 C
1.65
1.80 0.50 BSC
1.90
7,8 -
e k L N 0.20 0.30
C SEATING PLANE
SIDE VIEW
A3
0.40 8 4
0.50
8 2 3 Rev. 0 6/04
D2 (DATUM B) 1 2 D2/2
7
8
Nd NOTES:
6 INDEX AREA (DATUM A)
NX k
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D.
E2 E2/2
4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N N-1 NX b 8 e (Nd-1)Xe REF. BOTTOM VIEW (A1) NX (b) 5 SECTION "C-C" CC e FOR EVEN TERMINAL/SIDE TERMINAL TIP L C L 5 0.10 M C AB
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN9231.2 March 28, 2008

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